SPI

The Serial Peripheral Interface, or SPI, is a synchronous serial interface.   One of the key benefits of the SPI interface is that it provides much higher data transfer rates than UART and I2C interfaces.  Increased data speeds make SPI a popular interface for embedded systems that interface with large banks of non-volatile storage (SD and microSD).  The SPI bus is also used by modern PCs to load the BIOS.  While the SPI bus provides increased data throughput over I2C and UART, it also requires more pins than the UART and I2C interfaces.

So what makes SPI faster than a UART?  The SPI bus achieves higher data transfer rates because two interconnected devices share a common clock.  The two devices synchronize data transfers using a common clock and data is  transmitted on every clock edge.  There is no over sampling of the SPI bus.  This differs from a UART interface that must sample the data for several clock cycles to determine the logic value of each bit.

Monarch/Subordinate Configuration

A SPI bus is designed as a point-to-point interface.  This means that only two devices are interconnected by a single SPI bus.  The synchronous nature of SPI also requires that one of the devices generates a clock that will be used to determine when data is shifted out of one device and into the other.  The device that generates the clock is said to be the monarch device.  The devices that does not generate the clock is said to be the subordinate device.  Because the monarch device is the only device that can generate a clock, the monarch device determines when all data transactions occur.  In most cases, the monarch device is a microprocessor and the subordinate device is a device that provides a specific function to the embedded system ( LCD screen, non-volatile storage, accelerometer, etc).

The monarch -subordinate topology of the SPI bus is fundamentally different than that of a UART.  A UART interface is asynchronous.  Either end of a UART communication channel can initiate data transfer because transmitting and receiving data are completely independent and neither device is responsible for generating a shared clock signal.   The asynchronous nature of the UART interface is very handy for sensors that inform the microprocessor that an input to the system has changed.  A UART based sensor can transmit data to the microprocessor at any time.  A SPI based sensor does not have this ability.   Since the sensor is almost always a subordinate device, it cannot generate the synchronizing clock to transmit data to the monarch .  So how does the data get to the monarch ?

There are two solutions to this problem.  The first is that the monarch to periodically poll the sensor.  Like any polling based scheme, this method is simple but it also consumes clock cycles trying to determine if the sensor has important data.  The second approach is for the sensor to generate an interrupt on one of the external pins of the microprocessor.   When the sensor is trying to report data, it asserts the interrupt indicating that it requires attention.  The microprocessor must be configured to generate an interrupt when the sensor asserts a specific pin.  The interrupt service routine for the pin initiates a SPI data transfer and reads the data.

SPI Bus Specifics

The SPI interface consists of 4 dedicated pins.

CLK

The SPI clock determines the rate at which data transfer occur.  The maximum speed of the clock is determined by analyzing both the monarch and subordinate devices.  Each device will support a maximum clock rate.  The device with the slowest maximum clock rate determines the maximum clock speed.  The SPI clock is only active during data transfers.  When data is not being transferred, the clock will be idle.

MOSI

The Monarch Out/Subordinate In signal is used by the monarch device to transfer data to the subordinate device.  Data is transmitted most significant bit first.

MISO

The Monarch In/Subordinate Out signal is used by the monarch device to receive data from the subordinate device.  Data is transmitted most significant bit first.

/CS

The SPI interface requires an active low chip select to frame the number of bytes being transmitted.  Unlike the UART interface, there are no start or stop bits used to determine when data is valid.  The chip select frames the data being transmitted.  By eliminating the start and stop bits allow us to transmit 8 bits of data in 8 clock cycles .  The UART interface has to transmit 10 symbols for every 8 bits of data due to the start and stop bits.

 A SPI transaction consists of all the data being sent while the /CS line remains low.  The monarch SPI device controls the /CS line, but here may be situations where the /CS line is configured as a normal GPIO pin and software will determine the value on the line.   When sending a large amount of data in a single transaction, software may control the /CS line because the amount of data being transferred exceeds the capacity of the transmit FIFO.

The image below shows a screen capture of a SPI transaction

  ~CS1 (the chip select) is low for 32 clock cycles.  This tells us that the SPI transaction is 4 bytes long.  We can also observe that the monarch transmits 4 bytes of data on the MOSI line and receives 4 bytes of data on the MISO.  It is important to recognize that when using the SPI bus, the monarch always receives the same amount of data that it transmits.

SPI Modes

When interfacing with another device, the SPI bus must be configured so that the both devices agree  on two things: how the clock behaves during periods of inactivity and when to sample the data.  These two characteristics are commonly referred to as the clock phase and clock polarity.

The clock polarity determines if the clock is brought to logic 0 or logic 1 when data is not being sent.  If the polarity is set to 0, then the clock will be pulled to logic 0 when inactive.  When the polarity is set to 1, the clock will be pulled to logic 1 when inactive

The clock phase indicates on which edge the monarch will transmit the first bit of data.  If the phase is equal to 0, the monarch transfers the Most Significant Bit (MSB) on the first edge of the clock.  If the phase is equal to 1, the monarch will shift out the MSB on the second edge of the clock.

Using both the polarity and phase, we can define 4 different SPI modes (0 through 3).  Some devices support all 4 SPI modes, other will only support a single SPI mode.  The microprocessor will need to be configured for a SPI mode that is supported by the subordinate device.

The images below are taken from the TM4C123 data sheet.  They illustrate SPI mode 0 and SPI mode 3.  The dotted lines indicate on which clock edge the data is sampled.